Introduction
AMD today unveiled its 6th generation EPYC 9006 “Venice” and EPYC “Verona” server processors in the SP7 package. Both are powered by the company’s latest Zen 6 microarchitecture which aims to significantly increase the number of CPU cores and IPC compared to the current ‘Zen 5’, in addition to introducing a major I/O upgrade to the platform. Today the company is only announcing its EPYC server processors, Ryzen client processors powered by Zen 6 are expected later.
For starters, Zen 6 introduces the first major increase in core counts for the performance chipset since “Zen 2” from eight years ago. Built on the 2nm TSMC N2 foundry node, the CCD includes 12 Zen 6 performance cores in a single CPU core complex (CCX), sharing 48MB of L3 cache. This represents a 50% increase in the number of base and top-level caches.
The real story of the day, however, is the compact Zen 6c core. AMD claims to have given its compact core its largest generational increase in IPC and core count. AMD’s C cores are spiritually E cores, but are physically compacted P cores that feature the same basic components and core-level caches, but with limited clock speed headroom compared to conventional cores. With “Zen 6c”, AMD claims to have increased the IPC, maximum clock speed and core count of the Zen 6c chipset, significantly compared to the previous generation “Zen 5c” chipset.
AMD is introducing a new pure Zen 6c CCD, built on the same 2nm TSMC N2 foundry node as the Zen 6 chipset, increasing the number of cores per CCD to 32 cores. That’s not all, AMD has also quadrupled the onboard L3 cache for this CCD to a generous 128 MB. So not only is the cache doubled, but also the L3 cache per core has doubled from 2 MB/core to 4 MB. Since Zen 6 retains SMT like all previous generations of “Zen”, this CCD is 32 cores/64 threads, allowing AMD to build its latest EPYC Verano processors with a maximum number of cores of 256 cores/512 threads.
AMD claims a massive 20% IPC increase for Zen 6 compared to “Zen 5” in enterprise and cloud server workloads; and a 31% increase in IPC in AI workloads. It’s very important to note here that AMD is only testing EPYC-relevant benchmarks to arrive at these numbers, and the IPC increase for future Ryzen client processors powered by Zen 6 cores could be significantly different as these are evaluated on a very different set of benchmarks. It is also important to note here that Zen 6 and Zen 6c, like all previous versions of the standard and compacted cores of “Zen”, provide identical IPC, and the only thing that separates them is the clock speed limitations on the compacted core.
Big numbers are easy to repeat and hard to believe. A single Venice socket can hold up to 256 cores. It powers them from 16 channels of DDR5 memory, which at MRDIMM speeds equates to 1.6 TB/s of memory bandwidth per socket. It is the first x86 processor with PCIe Gen 6 and the first server processor of any type to support JEDEC-compliant MRDIMM. AMD claims 2.0x the SPECint 2026 throughput of the 5th gen “Turin” and 2.4x the floating point throughput.
AMD is planning its next generation of Ryzen desktop processors on the same Zen 6 chipset you’ll see throughout this article. However, today’s launch is purely focused on EPYC: the company hasn’t measured the performance of any consumer/client applications, and even its IPC calculations for Zen 6 are purely theoretical.
Venice SP7 platforms are available now. Microsoft Azure announced a preview of its HDv2 instances built on Venice, making it the first cloud to offer 6th generation EPYC. The rest of the family arrives until 2027.
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